The invention relates to a circuit arrangement for quantizing digital signals and filtering the quantization noise.
Oversampling digital-to-analog converters operating according to the sigma-delta method have an interpolation filter for increasing sample rate, a downstream circuit arrangement for quantizing and filtering the quantization noise (noise-shaping loop) and a digital-to-analog converter with a short input word length.
U.S. Pat. No. 5,369,403 discloses a sigma-delta digital-to-analog converter with a small quantization error, which has a first and second digital control loop for quantization. The second digital control loop processes the quantization error of the first digital control loop. The quantized output signals of the first and second digital control loops are respectively converted into a first and second analog signal by a first and second digital-to-analog converter. The second analog signal is filtered in an analog fashion and added to the first analog signal, which has only a small quantization error. The complicated analog filtering of the second signal and the errors in the analog addition, which limits the linearity of the converted analog signal, are disadvantageous in this process.
DE 197 22434C discloses a circuit having a plurality of digital control loops, the quantization error signal of a first control loop being fed as input signal to a second control loop, and a digital high-pass filter additionally being present at the output of the second control loop. The filtered output signal of the second control loop is, however, added to the input signal of the circuit and the quantization error filtered in the first control loop.
DE 197 22434C discloses a circuit having a plurality of digital control loops, the quantization error signal of a first control loop being fed as input signal to a second control loop, and a digital high-pass filter additionally being present at the output of the second control loop. The filtered output signal of the second control loop is, however, added to the input signal of the dircuit and the quantization error filtered in the first control loop.
The invention relates to a circuit arrangement for quantizing digital signals and filtering the quantization noise. The circuit arrangement has a multiplicity of series-connected digital control loops with quantizers. A first control loop of the series is fed the digital signals which have a first word length of m bits. The quantization error signal of each quantizer is filtered and fed back in the respective digital control loop. The quantization error signal of each quantizer is fed to a downstream digital control loop. The quantized output signal of the first digital control loop is adapted to a third word length of u bits, which is smaller than the first word length. Except for the quantized output signal of the first digital control loop, the quantized output signals of the digital control loops of the series are respectively filtered by a digital filter and are added in an adder to the quantized output signal of the first digital control loop of the series in order to delete the quantization errors, the output signal of said adder having a second word length of n bits and being the quantized output signal of the circuit arrangement. The quantization noise caused by the quantization error is advantageously reduced using digital means. A further advantage results from the exclusive use of digital means which permit an accuracy limited only by the word length of the computing circuits. Furthermore, digital means are simpler to use than analog means, particularly given integration of the circuit arrangement on a monolithic component.
The quantization error of the respective upstream digital control loop is deleted by the digital filtering of the output signal of each digital control loop apart from the first digital control loop and the summation of the output signals of each digital control loop. What remains is the quantization error of the last digital control loop of the series, since it is not followed by any further digital control loop for deleting the quantization error. It is advantageous in this case that even signals with a low oversampling of the basic signal can be quantized by this circuit arrangement with a very small quantization error. In such a case, the noise spectrum generated by a quantization error is filtered efficiently and deleted from the original useful signal spectrum of the sampled signal despite the useful signal spectra of the sampled signal which are obvious on the basis of a low sampling rate.
In a preferred embodiment, each digital filter has a high-pass filter. The noise spectrum, which is caused by the quantization error of the last digital control loop of the series circuit, is advantageously damped thereby at low frequencies and causes less interference to the spectral components of a useful signal, which are at low frequencies.
In a particularly preferred embodiment, each digital filter has two series-connected differentiators of first order. The simple design of each digital filter with digital means is advantageous. Only two subtractors and two time-delay elements are required for the design.
In a preferred embodiment, the quantizers quantize an input signal by cutting off the low-order bits of the input signal. The method of cutting off the low-order bits advantageously requires a very low outlay on circuitry.
In an alternative preferred embodiment, the quantizers quantize an input signal by rounding instead of by cutting off. This method is certainly more complicated in terms of circuitry than quantization by cutting off, but returns more accurate results.
Each digital control loop preferably has a limiter upstream of the quantizer, a filter structure for filtering the quantization error signal, and an adder which adds an input signal to the filtered quantization error signal. In this case, a limiter prevents overshooting of the range of values prescribed by the downstream circuit structures.
It is particularly preferred for each digital control loop to be at most of second order, in order to avoid stability problems. Orders higher than the second require means for improving the stability, as a result of which the outlay on circuitry for the digital control loop increases.